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AI infrastructure spending is pulling serious weight in the U.S. economy, with chips, software, and data centers accounting for nearly 40% of GDP growth so far in 2025. Three companies sit at the less-visible end of that wave: Aehr Test Systems, which qualifies high-power chips before they reach hyperscale facilities; ASE Technology, the world’s largest outsourced chip packager now betting heavily on 3D IC and chiplet assembly; and Camtek, whose inspection tools underpin advanced packaging and high-bandwidth memory lines, with roughly 80% of its $600 million-plus in 2026 year-to-date AI infrastructure orders scheduled into 2027.
What this means for your business
The story the article is really telling, beneath the stock framing, is a supply-chain concentration story. Every hyperscaler’s GPU procurement plan runs through the same narrow band of test, packaging, and inspection capacity. If your infrastructure roadmap assumes continued GPU availability at current lead times, the health of companies like ASE and Camtek is not a financial curiosity. It is a constraint you are already living inside, whether your procurement team tracks it or not.
The silicon photonics angle on Aehr is worth holding separately. Optical interconnects inside data centers, where light replaces copper wires to move data faster between chips, are moving from research to production faster than most enterprise architects have priced in. Aehr’s burn-in equipment, which stress-tests chips to catch failures before deployment, is a gating factor for that transition. Repeat system orders and forecasts for additional test cells suggest the optical build-out is real and accelerating, not a 2028 story.
ASE’s capital push into advanced packaging, specifically 3D IC stacking and chiplet integration, deserves attention because it determines which chip designs are even manufacturable at scale. A chiplet is a modular chip design where multiple smaller dies are assembled together, the way you might assemble a PC from components rather than buying a single pre-built unit, and it is the architecture underpinning the next generation of AI accelerators. If ASE’s capacity expansion hits funding or execution friction, GPU roadmaps slip. That is the pressure point the article gestures at without fully naming.
The falsification condition for all three names is the same: if hyperscaler capex plateaus or shifts toward in-house chip designs that bypass third-party packaging and test, the demand thesis compresses fast. The leading indicator to watch is not earnings, it is order backlog duration. Camtek’s 2026 orders already scheduled into 2027 suggest the cycle has more runway than the bears argue. I would revise that view if delivery schedules started pulling back toward same-year fulfillment, which would signal customers hedging against their own AI deployment timelines.
Concept deep-dive: High-Bandwidth Memory (HBM)
High-bandwidth memory stacks multiple memory chips vertically on top of each other and connects them through the silicon itself, the way a multi-story building uses internal elevators rather than external roads. It exists because modern AI accelerators process data faster than conventional memory can feed them, creating a bottleneck. Camtek’s inspection tools qualify HBM stacks before they ship, making it a direct dependency for GPU manufacturers. Yield problems at the HBM inspection stage propagate directly into AI chip availability.
Based on reporting from 3 AI Infrastructure Stocks Worth Watching As Data Center Spending Climbs, originally published 2026-10-10 15:49:00.
